Mobile phones are constrained in how many signal tines can be sent between sections of flip, clam shell and slide phones. MIPI interfaces have minimized the signal lines by serializing the transmitted data commonly found in such phones. An MIPI interface, see below, typically has a single clock “lane,” CLK, and two data “lanes,” D1 and D2, that carry serial data. These three lanes carry signals on pairs of wires, the signals often being differential. Since the MIPI is a point-to-point interface, however, a separate GPIO (general purpose I/O) signal is employed with an analog switch if two sources are sending data to an MIPI interface.
“Coupled,” and “connected” are used interchangeably herein and may include other relatively passive components that do not substantially alter the functions being described.
FIG. 1 illustrates a processor 8, with a single camera MIPI interface 2 communicating with two image sensors 4 and 6 via an analog switch 10. Here item 4 is a mega-pixel snapshot image sensor and item 6 is a low resolution video image sensor. The MIPI interface 2 is shown within an application processor 8, but it may be shown as a stand alone controller. The application processor also controls a GPIO, a General Purpose Input-Output interface 12. The GPIO 12 provides the SEL signal that selects which of the two sensors conies through the analog switch 10.
Some issues with the prior art include the use of an additional GPIO interface that must be separately addressed by the processor 8.
The MIPI specification is known to those skilled in the art. That specification is briefly described below to provide an environment framework for the present invention. More detailed information can be obtained by referring to the specification itself.
An MIPI interface has a high speed (HS) operation where D1 and D2 data lanes operate as a differential pair of wires to indicate a logic 1 or 0. An MIPI interface also has a Low Power (LP) and a ULP (Ultra Low Power) state or mode of operation, where each of the two wires, referenced as Dp and Dn, in the data and the clock lanes are driven independently. So in LP or ULP operation there are four possible states of the Dp and Dn wires: 11, 10, 01, and 00. Note in this notation, the values of each Dp and Dn occur at the same time In HS operation, if both the Dp and Dn signals of a data or a clock lane are driven high, for a minimum required time, that lane drives the MIN into a STOP or CONTROL state.
When in the STOP state the sequence of data on the Op, Dn wires may define a request to enter into other states. For example a data lane sequence of LP-11>10>00>01>00 will enter the ESCAPE STATE. Once in the ESCAPE mode, an eight bit command may be sent via “Spaced-One-Hot” coding. This coding means that sending a logic 1, termed Mark-1 or a logic 0, termed a Mark-0, is interleaved with a Space state (a zero), where each of the Mark's and Space consists of two parts. That is a Mark-1 is defined as a LP-10 (Dp=1, Dn=0), and a Mark-0 is a LP-01 and a Space is a LP-00, For example, sending a “one” via a LP MIPI interface in the ESCAPE mode would be the following sequence: LP-10>00; and sending a “zero” sequence would be LP-01>00.
In addition a clock lane may enter a STOP mode by driving both Dp and Dn of the clock lane high, From the STOP state the clock may enter the ULPS state by LP-01 or the HS state by LP-10, as discussed below.